The present invention relates generally to an integrated circuit (IC) design, and, more particularly, to designs of power supply to built-in test circuitries in ICs.
As semiconductor processing technology has progressed to deep submicron technologies, more and more devices can be packed in a single chip. Each device may have a small amount of leakage, but an accumulative leakage from a great number of devices can pose a problem, especially to a chip used in a hand-held equipment powered by batteries.
Many complicated chips have built-in self test (BIST) circuitries to facilitating the testing of the chips prior to shipping them to customers. These BIST circuitries are used only during the chip testing phase, once a chip passes the test and is shipped to a customer, those BIST circuitries will not be used any more. But devices in the BIST circuitries are still coupled to a power supply, hence still produce leakage, even they have no functions during the chip operations.
A traditional way to reduce leakage from BIST circuitries is to use devices with higher threshold voltage to build the BIST circuitries, as speed requirements for the BIST is normally very lose. High threshold voltage devices have lower leakage, but switching speed is also slower than their lower threshold voltage counterparts. But this method does not completely cut off the leakage, and some time it may require additional processing steps.
So what is desired is a design that can reduce the number of devices, which can contribute to the overall leakage to the minimum.